Technical Field
This disclosure relates to processor cache operation, and more particularly to cache management mechanisms.
Description of the Related Art
Modern processors use a number of cache memory hierarchies in an effort to expedite data retrieval from main memory. In particular, most all processor cores will have at least a level one (L1) cache that is proximal to the core. In many cases, and especially in multi-core designs, a processor will also have a level two (L2) cache, and in some cases a level three (L3) cache. The L2 and L3 caches are in many cases shared among the various processor cores. The multiple cache hierarchies allow a processing system to keep copies of data that is accessed frequently in the local faster cache memory hierarchy, rather than having to access main memory which is typically slower.
Additional levels of cache memories as well as increased sizes of cache memories have contributed to power consumption in processing systems. In many applications, such as, e.g., mobile computing, additional power consumption may lead to a decrease in battery life. Many processing systems attempt to reduce power consumption by removing power (commonly referred to as “power gating”) to unused functional blocks within the system. For example, cache memories may be power gated when processor cores are inactive and not accessing the memories.